1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as a memory, a photoelectric device and a signal processing device mounted on various electronic equipment and a method for manufacturing it, and more particularly to a semiconductor device incorporating electrostatic capacitive element and a method for manufacturing it.
2. Related Background Art
There is a semiconductor integrated circuit incorporating a number of electrostatic capacitive elements. Recently, along with the emergence of higher density and higher speed integrated circuits, a capacitive element of smaller size and with larger capacity is sought.
FIG. 1 is a typical cross-sectional view of a MOS capacitor generally used in an integrated circuit, and FIG. 2 is its equivalent circuit. This MOS capacitor comprises a lower electrode layer of an n+ layer 103 formed on an n- layer 102 buried into a p-type substrate 101, an upper electrode 105 via a dielectric layer 104 and an extraction electrode 106 from the n+ layer. An A terminal and a B terminal in the equivalent circuit correspond to the upper electrode 105 and the lower extraction electrode 106, respectively. As shown in the equivalent circuit, since an electric conductor such as an n+ diffusion layer is used as the lower electrode, parasitic devices such as a diode D and a capacitor Ccs are produced relative to the substrate, and there is a resistive component R1 due to the n+ diffusion layer between a capacitor C.sub.1 and the B terminal. Also, as the upper electrode, Al or polysilicon is generally used, but when polysilicon is used, a resistive component R2 due to polysilicon is added between the A terminal and the capacitor C.sub.1.
Accordingly, when MOS capacitor is used, as parasitic devices such as a resistor, capacitor and diode are contained other than the capacitor C.sub.1, the frequency characteristics of the MOS capacitor are restricted under the influence of those parasitic devices.
Also, when one terminal of capacitive element is used at a high impedance, the capacity division with C.sub.1 and Ccs is caused owing to the parasitic element Ccs.
Moreover, depending on the polarity of applied voltage, the capacity value is changed with the voltage due to the CV characteristics of MOS structure.
FIG. 3 is a typical cross-sectional view of a pn junction capacitor generally used for an integrated circuit, and FIG. 4 is its equivalent circuit. This capacitor comprises an n layer 102, a p layer 107 and n+ layers 103, 108 formed on a p-type substrate 101, and electrodes 109, 110 opposed via a dielectric layer 104.
Numerals of a structure as shown in FIG. 3 correspond to those of terminals in the equivalent circuit. The capacitance between terminals X and Y is C.sub.2 +C.sub.3, but any pn junction can be used as capacitor.
As the pn junction capacitor contains parasitic resistance and parasitic capacitance, the frequency characteristics are restricted due to their influences, and further the capacitance value largely depends on the voltage. Moreover, it can not be used except when the pn junction becomes bias.
FIG. 5 is a typical cross-sectional view of a capacitive element of metal-insulation film-metal structure which has been devised to improve disadvantages of the MOS capacitor or pn junction capacitor as above described.
This capacitive element comprises a surface metal (lower electrode) 202 formed on a semiconductor substrate 201, an interlayer insulation film 203, an upper layer metal (upper electrode) 204, and a thin insulation film (dielectric layer) 205 which is a capacitive portion.
As metal films of the upper and lower layers, Al or Al alloy formed by the magnetron sputtering method, tungsten, or tungsten formed by the chemical vapor deposition (CVD) method are used. As the thin insulation film 205 serving as a capacitor, SiO.sub.2, Si.sub.3 N.sub.4, or Ta.sub.2 O.sub.5 formed by CVD, Al.sub.2 O.sub.3 formed by anodizing, or a laminate made of a combination of those films can be used.
In this capacitive element, there is an advantage that parasitic capacitance or parasitic resistance may not be produced. However, in a conventional technology, the surface of electrode was coarse, so that it was difficult to increase the electrostatic capacity per unit area of capacitive element. That is, on an electrode surface formed by the conventional technology, hillocks 202A might be produced as shown on larger scale in FIG. 5, so that a problem arose such that if the thickness of dielectric layer 205 is made thinner to increase the electrostatic capacitance per unit area of capacitive element, the dielectric layer 205 may be broken at a position where hillock 202A is produced, or becomes extremely thin and thus has a lower electrical withstand voltage. In other words, a metal film formed by a conventional method such as sputtering method or CVD method became quite irregular on the surface of metal film, because the stress built up in the film might be dispersed in the form of hillocks with the heat processing after deposition, whereby it was difficult to form a thin insulation layer.
In a highly integrated circuit system, it is required to form the thin insulation layer uniformly at high dielectric constant. Particularly, with a capacitive element of Al-insulation layer-Al structure, if Al.sub.2 O.sub.3 with a dielectric constant of 8 to 10 can be used as the insulation layer by anodizing Al, the degree of integration can be greatly improved. However, as described above, with the conventional technology, there were too many irregularities on the surface of Al, so that it was indispensable to form Al.sub.2 O.sub.3 uniformly at practical yield.
On the other hand, as an electrostatic capacitive element used for a dynamic RAM, a circuit as shown in FIG. 6 is known in which a capacitor is connected to the drain side of MOSFET. FIG. 7 is one of the device structures for implementing that circuit, referred to as a stack type This structure includes a pMOSFET having a polysilicon gate 23 on a gate oxide film 22 formed on a p-type substrate 21, a source 24, a drain 25, a source electrode 26, a field oxide film 27, an oxide film 2 and an interlayer insulation film 29, and a capacitor composed of a polysilicon 30 provided in contact with the drain of pMOSFET, and a further polysilicon 32 provided via a dielectric film 31. A trench type as shown in FIG. 8 and a fin type as shown in FIG. 9 are obtained by deforming the shapes of respective polysilicon layers 30A, 32A and 30B, 32B as shown, in order to increase the capacitance of stack-type capacitor and decrease its size.
Apart from a desired improvement of electrostatic capacitive element itself as previously described, the increase of capacitance and the reduction of element area for capacitor became a large technical problem. However, in the stack-type as described above, the increase of capacitance and the reduction of element area for capacitor are not consistent, in the trench type, there is a problem of leakage in the capacitor, and in the fin type, there is a problem that the manufacturing process becomes complex because the shape of polysilicon is complex, so that it was difficult to provide a memory cell at lower price with increased degree of integration.
That is, with the conventional technique, as the constitution or manufacturing method for capacitor was not sufficient, it was difficult to form a capacitor with small occupying area and large capacitance at good yield.
In a semiconductor circuit, a storage element (thereafter referred to as a memory cell) having a circuit configuration as shown in FIG. 10 is known. A typical cross-sectional view of such a memory cell is shown in FIG. 11. As shown in FIG. 11, a capacitor C as capacitive element incorporated into the memory cell is constituted of a lower electrode 30, an upper electrode 32, and a dielectric film 31 formed between both electrodes 30, 32.
When the higher integration is required for such memory cell, it is necessary to reduce the plane area of capacitor C as capacitive portion in each bit. In order to operate the memory cell normally, it is necessary to build up the quantity of electric charge as much as about 200 fc in the capacitor C to secure the resistance against soft error due to the .alpha. ray emitted from a ceramic package of DRAM, for instance. If setting the power voltage at 5 V with this quantity of charge, and representing the capacitance between source and earth for the capacitor C as Cs, then EQU Cs.gtoreq.40 fF
When the dielectric film 31 is a general Si oxide film, it is known that the electric field applicable to the dielectric film 31 is E&lt;about 5 MV/cm because of the reliability for the Si oxide film. Thus, when a method for applying a voltage half the power voltage is used, the thickness of Si oxide film that can be sufficiently used as the dielectric film is presumed to be 50 .ANG.. Since the dielectric constant .epsilon. r of Si oxide film is 3.7, it is necessary to secure the plane area of capacitor C as large as 6 .mu.m.sup.2 or more, in order to realize Cs.gtoreq.40 fF. A memory cell comprising a capacitor having such a large plane area can not meet the recent requirements of higher degree of integration as above described. Thereby, with the capacitor C of laminated structure in the shape of downward or upward convex as shown in FIG. 11, for example, the necessary capacitance was secured by increasing the surface area without enlarging the projection plane area of capacitor C.